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| 74VHC16374 16-BIT D-TYPE FLIP FLOP WITH 3-STATE OUTPUTS NON INVERTING s s s s s s s s s s HIGH SPEED: fMAX = 185 MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 A (MAX.) at TA=25C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 16374 IMPROVED LATCH-UP IMMUNITY LOW NOISE: VOLP = 0.9V (MAX.) TSSOP ORDER CODES PACKAGE TSSOP TUBE T&R 74VHC16374TTR PIN CONNECTION DESCRIPTION The 74VHC16374 is an advanced high-speed FLIP FLOP with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. These 16 bit D-TYPE flip-flop is controlled by two clock inputs (CK) and two output enable inputs (nOE). The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock, the Q outputs will be set to the logic state that were setup at the D inputs. While the (OE) input is low, the outputs will be in a normal logic state (high or low logic level); while OE is high, the outputs will be in a high impedance state. The output control does not affect the internal operation of flip-flops; that is, the old data can be retained or the new data can be entered even while the outputs are off. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. February 2003 1/11 74VHC16374 INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1 2, 3, 5, 6, 8, 9, 11, 12 13, 14, 16, 17, 19, 20, 22, 23 24 SYMBOL 1OE 1Q0 to 1Q7 2Q0 to 2Q7 2OE NAME AND FUNCTION 3 State Output Enable Input (Active LOW) 3-State Outputs 3-State Outputs IEC LOGIC SYMBOLS 3 State Output Enable Input (Active LOW) 25 2CK Clock Input (LOW-to-HIGH Edge Trigger) 36, 35, 33, 32, 2D0 to 2D7 Data Inputs 30, 29, 27, 26 47, 46, 44, 43, 1D0 to 1D7 Data Inputs 41, 40, 38, 37 48 1CK Clock Input (LOW-to-HIGH Edge Trigger) 4, 10, 15, 21, GND Ground (0V) 28, 34, 39, 45 7, 18, 31, 42 VCC Positive Supply Voltage TRUTH TABLE INPUTS OE H L L L X : Don't Care Z : High Impedance OUTPUTS D X X L H Q Z NO CHANGE L H CK X 2/11 74VHC16374 LOGIC DIAGRAM This logic diagram has not to be used to estimate propagation delays ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Parameter Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 - 20 20 25 75 -65 to +150 300 Unit V V V mA mA mA mA C C ICC or IGND DC VCC or Ground Current Storage Temperature Tstg TL Lead Temperature (10 sec) Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO Top dt/dv Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time (note 1) (VCC = 3.3 0.3V) (VCC = 5.0 0.5V) Parameter Value 2 to 5.5 0 to 5.5 0 to VCC -55 to 125 0 to 100 0 to 20 Unit V V V C ns/V 1) VIN from 30% to 70% of VCC 3/11 74VHC16374 DC SPECIFICATIONS Test Condition Symbol Parameter VCC (V) 2.0 3.0 to 5.5 2.0 3.0 to 5.5 2.0 3.0 4.5 3.0 4.5 VOL Low Level Output Voltage 2.0 3.0 4.5 3.0 4.5 IOZ High Impedance Output Leakage Current Input Leakage Current Quiescent Supply Current 5.5 0 to 5.5 5.5 IO=-50 A IO=-50 A IO=-50 A IO=-4 mA IO=-8 mA IO=50 A IO=50 A IO=50 A IO=4 mA IO=8 mA VI = VIH or VIL VO = VCC or GND VI = 5.5V or GND VI = VCC or GND TA = 25C Min. 1.5 0.7VCC 0.5 0.3VCC 1.9 2.9 4.4 2.58 3.94 0.0 0.0 0.0 0.1 0.1 0.1 0.36 0.36 0.25 0.1 4 2.0 3.0 4.5 1.9 2.9 4.4 2.48 3.8 0.1 0.1 0.1 0.44 0.44 2.5 1 40 Typ. Max. Value -40 to 85C Min. 1.5 0.7VCC 0.5 0.3VCC 1.9 2.9 4.4 2.4 3.7 0.1 0.1 0.1 0.55 0.55 5 1 40 A A A V V Max. -55 to 125C Min. 1.5 0.7VCC 0.5 0.3VCC V V Max. Unit VIH High Level Input Voltage Low Level Input Voltage High Level Output Voltage VIL VOH II ICC 4/11 74VHC16374 AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3ns) Test Condition Symbol Parameter VCC (V) 3.3(*) 3.3(*) 5.0 tPZL tPZH Output Enable Time (**) Value TA = 25C Min. Typ. 9 10.6 5.4 6.9 8 9.6 5.1 6.6 11.8 6.1 5 5 4.5 3 2 2 80 130 130 185 1.5 1 Max. 15 16.2 9.1 10.1 13 14.9 9.1 10.1 15.5 10.5 -40 to 85C Min. 1 1 1 1 1 1 1 1 1 1 5 5 4 3 2 2 70 110 1.5 1 Max. 17 18.5 10.1 11.5 15 16 10 11.5 17 11.5 -55 to 125C Min. 1 1 1 1 1 1 1 1 1 1 5 5 4 3 2 2 70 110 1.5 1 Max. 17 18.5 10.1 11.5 15 16 10 11.5 17 11.5 ns ns ns Unit CL (pF) 15 50 15 50 15 50 15 50 50 50 tPLH tPHL Propagation Delay Time CK to Q 5.0(**) 3.3 (*) 3.3(*) 5.0(**) 5.0 (**) tPLZ tPHZ tw ts th fMAX tOSLH tOSHL Output Disable Time Pulse Width (CK) HIGH or LOW Setup Time Dn to CK HIGH or LOW Hold Time Dn to LE HIGH or LOW Maximum Clock Frequency Output to Output Skew time (note 1) 3.3(*) 5.0 (**) ns 3.3(*) 5.0(**) 3.3(*) 5.0 (**) ns ns 3.3(*) 5.0 (**) ns MHz 3.3(*) 5.0(**) 3.3(*) 5.0 (**) 50 50 ns (*) Voltage range is 3.3V 0.3V (**) Voltage range is 5.0V 0.5V Note 1 : Parameter guaranteed by design. tsoLH = |tpLHm - tpLHn|, tsoHL = |tpHLm - tpHLn| CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter VCC (V) TA = 25C Min. Typ. 2.5 4 5.0 fIN = 10MHz 21 Max. 10 Value -40 to 85C Min. Max. 10 -55 to 125C Min. Max. 10 pF pF pF Unit CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance (note 1) 1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/16 (per Latch) 5/11 74VHC16374 DYNAMIC SWITCHING CHARACTERISTICS Test Condition Symbol Parameter VCC (V) 5.0 TA = 25C Min. Typ. 0.6 -0.9 CL = 50 pF 3.5 -0.6 Max. 0.9 V Value -40 to 85C Min. Max. -55 to 125C Min. Max. Unit VOLP VOLV VIHD VILD Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3) 5.0 V 5.0 1.5 V 1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n-1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to 5.0V. Inputs under test switching: 5.0V to threshold (V ILD), 0V to threshold (VIHD), f=1MHz. TEST CIRCUIT TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ CL = 15/50 pF or equivalent (includes jig and probe capacitance) RL = R1 = 1K or equivalent RT = ZOUT of pulse generator (typically 50) SWITCH Open VCC GND 6/11 74VHC16374 WAVEFORM 1 PROPAGATION DELAYS, SETUP AND HOLD TIMES, MAXIMUM CLOCK FREQUENCY (f=1MHz; 50% duty cycle) WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle) 7/11 74VHC16374 WAVEFORM 3 : CLOCK PULSE WIDTHS (f=1MHz; 50% duty cycle) 8/11 74VHC16374 TSSOP48 MECHANICAL DATA mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0 0.50 6.0 0.5 BSC 8 0.75 0 0.020 0.17 0.09 12.4 8.1 BSC 6.2 0.236 0.0197 BSC 8 0.030 0.05 0.9 0.27 0.20 12.6 0.0067 0.0035 0.488 0.318 BSC 0.244 TYP MAX. 1.2 0.15 0.002 0.035 0.011 0.0079 0.496 MIN. TYP. MAX. 0.047 0.006 inch A A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 7065588C 9/11 74VHC16374 Tape & Reel TSSOP48 MECHANICAL DATA mm. DIM. MIN. A C D N T Ao Bo Ko Po P 8.7 13.1 1.5 3.9 11.9 12.8 20.2 60 30.4 8.9 13.3 1.7 4.1 12.1 0.343 0.516 0.059 0.153 0.468 TYP MAX. 330 13.2 0.504 0.795 2.362 1.197 0.350 0.524 0.067 0.161 0.476 MIN. TYP. MAX. 12.992 0.519 inch 10/11 74VHC16374 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2003 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com 11/11 |
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